The Design Warrior's Guide to FPGAs : Devices, Tools and Flows

Preface ix Acknowledgments xi Introduction 1(8) What are FPGAs? 1(1) Why are FPGAs of interest? 1(3) What can FPGAs be used for? 4(2) What's in this book? 6(1) What's not in this book? 7(1) Who's this book for? 8(1) Fundamental Concepts 9(16) The key thing about FPGAs 9(1) A simple programmable function 9(1) Fusible link technologies 10(2) Antifuse technologies 12(2) Mask-programmed devices 14(1) PROMs 15(2) EPROM-based technologies 17(2) EEPROM-based technologies 19(1) FLASH-based technologies 20(1) SRAM-based technologies 21(1) Summary 22(3) The Origin of FPGAs 25(32) Related technologies 25(1) Transistors 26(1) Integrated circuits 27(1) SRAMs, DRAMs, and microprocessors 28(1) SPLDs and CPLDs 28(14) ASICs (gate arrays, etc.) 42(7) FPGAs 49(8) Alternative FPGA Architectures 57(42) A word of warning 57(1) A little background information 57(2) Antifuse versus SRAM versus 59(7) Fine-, medium-, and coarse-grained architectures 66(2) MUX- versus LUT-based logic blocks 68(5) CLBs versus LABs versus slices 73(4) Fast carry chains 77(1) Embedded RAMs 78(1) Embedded multipliers, adders, MACs, etc 79(1) Embedded processor cores (hard and soft) 80(4) Clock trees and clock managers 84(5) General-purpose I/O 89(3) Gigabit transceivers 92(1) Hard IP, soft IP, and firm IP 93(2) System gates versus real gates 95(3) FPGA years 98(1) Programming (Configuring) an FPGA 99(16) Weasel words 99(1) Configuration files, etc. 99(1) Configuration cells 100(1) Antifuse-based FPGAs 101(1) SRAM-based FPGAs 102(3) Using the configuration port 105(6) Using the JTAG port 111(2) Using an embedded processor 113(2) Who Are All the Players? 115(6) Introduction 115(1) FPGA and FPAA vendors 115(1) FPNA vendors 116(1) Full-line EDA vendors 116(1) FPGA-specialist and independent EDA vendors 117(1) FPGA design consultants with special tools 118(1) Open-source, free, and low-cost design tools 118(3) FPGA Versus ASIC Design Styles 121(12) Introduction 121(1) Coding styles 122(1) Pipelining and levels of logic 122(4) Asynchronous design practices 126(1) Clock considerations 127(2) Register and latch considerations 129(1) Resource sharing (time-division multiplexing) 130(1) State machine encoding 131(1) Test methodologies 131(2) Schematic-Based Design Flows 133(20) In the days of yore 133(1) The early days of EDA 134(7) A simple (early) schematic-driven ASIC flow 141(2) A simple (early) schematic-driven FPGA flow 143(5) Flat versus hierarchical schematics 148(3) Schematic-driven FPGA design flows today 151(2) HDL-Based Design Flows 153(26) Schematic-based flows grind to a halt 153(1) The advent of HDL-based flows 153(8) Graphical design entry lives on 161(2) A positive plethora of HDLs 163(9) Points to ponder 172(7) Silicon Virtual Prototyping for FPGAs 179(14) Just what is an SVP? 179(1) ASIC-based SVP approaches 180(7) FPGA-based SVPs 187(6) C/C++ etc. -Based Design Flows 193(24) Problems with traditional HDL-based flows 193(3) C versus C++ and concurrent versus sequential 196(2) SystemC-based flows 198(7) Augmented C/C++-based flows 205(4) Pure C/C++-based flows 209(4) Different levels of synthesis abstraction 213(1) Mixed-language design and verification environments 214(3) DSP-Based Design Flows 217(22) Introducing DSP 217(1) Alternative DSP implementations 218(7) FPGA-centric design flows for DSPs 225(11) Mixed DSP and VHDL/Verilog etc. environments 236(3) Embedded Processor-Based Design Flows 239(20) Introduction 239(2) Hard versus soft cores 241(4) Partitioning a design into its hardware and software components 245(2) Hardware versus software views of the world 247(2) Using an FPGA as its own development environment 249(1) Improving visibility in the design 250(1) A few coverification alternatives 251(6) A rather cunning design environment 257(2) Modular and Incremental Design 259(8) Handling things as one big chunk 259(2) Partitioning things into smaller chunks 261(3) There's always another way 264(3) High-Speed Design and Other PCB Considerations 267(10) Before we start 267(1) We were all so much younger then 267(2) The times they are a-changing 269(3) Other things to think about 272(5) Observing Internal Nodes in an FPGA 277(10) Lack of visibility 277(1) Multiplexing as a solution 278(2) Special debugging circuitry 280(1) Virtual logic analyzers 280(2) Virtual Wires 282(5) Intellectual Property 287(6) Sources of IP 287(1) Handcrafted IP 287(3) IP core generators 290(1) Miscellaneous stuff 291(2) Migrating ASIC Designs to FPGAs and Vice Versa 293(6) Alternative design scenarios 293(6) Simulation, Synthesis, Verification, etc. Design Tools 299(44) Introduction 299(1) Simulation (cycle-based, event-driven, etc.) 299(15) Synthesis (logic/HDL versus physically aware) 314(5) Timing analysis (static versus dynamic) 319(3) Verification in general 322(4) Formal verification 326(12) Miscellaneous 338(5) Choosing the Right Device 343(10) So many choices 343(1) If only there were a tool 343(2) Technology 345(1) Basic resources and packaging 346(1) General-purpose I/O interfaces 347(1) Embedded multipliers, RAMs, etc. 348(1) Embedded processor cores 348(1) Gigabit I/O capabilities 349(1) IP availability 349(1) Speed grades 350(1) On a happier note 351(2) Gigabit Transceivers 353(20) Introduction 353(1) Differential pairs 354(3) Multiple standards 357(1) 8-bit/10-bit encoding, etc. 358(3) Delving into the transceiver blocks 361(1) Ganging multiple transceiver blocks together 362(2) Configurable stuff 364(3) Clock recovery, jitter, and eye diagrams 367(6) Reconfigurable Computing 373(8) Dynamically reconfigurable logic 373(1) Dynamically reconfigurable interconnect 373(1) Reconfigurable computing 374(7) Field-Programmable Node Arrays 381(16) Introduction 381(2) Algorithmic evaluation 383(1) picoChip's picoArray technology 384(4) QuickSilver's ACM technology 388(7) It's silicon, Jim, but not as we know it! 395(2) Independent Design Tools 397(10) Introduction 397(1) ParaCore Architect 397(4) The Confluence system design language 401(5) Do you have a tool? 406(1) Creating an Open-Source-Based Design Flow 407(12) How to start an FPGA design shop for next to nothing 407(1) The development platform: Linux 407(4) The verification environment 411(2) Formal verification 413(3) Access to common IP components 416(1) Synthesis and implementation tools 417(1) FPGA development boards 418(1) Miscellaneous stuff 418(1) Future FPGA Developments 419(10) Be afraid, be very afraid 419(1) Next-generation architectures and technologies 420(6) Don't forget the design tools 426(1) Expect the unexpected 427(2) Appendix A: Signal Integrity 101 429(14) Before we start 429(1) Capacitive and inductive coupling (crosstalk) 430(1) Chip-level effects 431(7) Board-level effects 438(5) Appendix B: Deep-Submicron Delay Effects 101 443(22) Introduction 443(1) The evolution of delay specifications 443(2) A potpourri of definitions 445(4) Alternative interconnect models 449(3) DSM delay effects 452(12) Summary 464(1) Appendix C: Linear Feedback Shift Registers 101 465(20) The Ouroboras 465(1) Many-to-one implementations 465(3) More taps than you know what to do with 468(2) Seeding an LFSR 470(2) FIFO applications 472(2) Modifying LFSRs to sequence 2n values 474(1) Accessing the previous value 475(1) Encryption and decryption applications 476(1) Cyclic redundancy check applications 477(2) Data compression applications 479(1) Built-in self-test applications 480(2) Pseudorandom-number-generation applications 482(1) Last but not least 482(3) Glossary 485(40) About the Author 525(2) Index 527