Verilog for Digital Design

Preface vii To Those About to Study Verilog vii To Teachers of Verilog vii About the Book ix Chapter Overview ix Accompanying Resources ix Formatting x Acknowledgments x About the Authors x Contents xiii Introduction 1(8) Digital Systems 1(1) Hardware Description Languages 2(4) HDLs for Design and Synthesis 6(3) Combinational Logic Design 9(26) And, Or, and Not Gates 9(9) Modules and Ports 9(2) Module Procedures---always 11(2) Simulation and Testbenches---A First Look 13(2) Variables and nets 15(1) Module procedures---initial 15(1) Delay control 16(1) Comments 17(1) Combinational Circuit Structure 18(5) Module Instantiations 18(2) Port Connections 20(1) Simulating The Circuit 21(2) Top-Down Design---Combinational Behavior to Structure 23(9) Procedures with If-Else Statements 25(3) Multiple Module Descriptions for One Module 28(1) Common Pitfalls 29(1) Missing inputs from event control expression 29(1) Outputs not assigned on every pass 30(2) Hierarchical Circuits 32(2) Using Modules as Instances 32(2) Built-in Logic Gates 34(1) Sequential Logic Design 35(30) Register Behavior 35(8) Vectors 35(2) Constant Numbers 37(1) Synchronous Storage Using a reg Variable 37(1) Testbenches with Clocks 38(2) Common Pitfalls 40(1) Using an always procedure instead of an initial procedure 40(1) Not including any delay control or event control in an always procedure 40(1) Not initializing all input ports 41(1) Not declaring an identifier used in a port connection 42(1) Finite-State Machines (FSMs)---Sequential Behavior 43(6) Multiple Always Procedures and Shared Variables 43(1) Parameters (Constants) 44(1) Procedures with Case Statements 44(2) Self-Checking Testbenches 46(3) Top-Down Design---FSMs to Controller Structure 49(4) Common Pitfall 51(1) Not assigning outputs in every state 51(2) More Simulation Concepts 53(6) The Simulation Cycle 53(3) Scheduled Events 56(3) Resets 59(3) Describing Safe FSMs 62(3) Datapath Components 65(32) Multifunction Registers 65(4) Continuous Assignment Statement 66(2) Common Pitfall 68(1) Not using a begin-end block with every if statement 68(1) Adders 69(5) Built-in Arithmetic Operations 69(3) Concatenation 72(1) Blocking Versus Non-Blocking Assignments 72(1) Left-Side Concatenation 73(1) Shift Registers 74(11) Procedures with For Loop Statements 76(1) Integer Variables 77(1) Relational, Logical, and Equality Operators 78(1) File Input and Output 79(1) Functions and tasks 80(1) File input and output procedures 81(1) While loops 82(1) Common Pitfall 83(1) Creating a loop that cannot be unrolled during synthesis 83(2) Comparators 85(3) Unsigned and Signed Numbers 85(2) Common Pitfall 87(1) Unintentional use of one of Verilog's many automatic conversions 87(1) Register Files 88(9) Using High-Impedance Values 90(1) Conditional Operator ``?'' 91(2) Multiple Drivers of One Net 93(2) Arrays 95(1) Common Pitfall 96(1) Confusing bitwise and logical operators 96(1) Register-Transfer Level (RTL) Design 97(32) High-Level State Machine (HLSM) Behavior 97(5) Top-Down Design---HLSM to Controller and Datapath 102(7) Describing a State Machine using One Procedure 109(3) Improving Timing Realism 112(2) Delay Control on Right Side of Assignment Statements 112(2) Algorithmic-Level Behavior 114(5) Top-Down Design---Converting Algorithmic-Level Behavior to RTL 119(4) Automated Synthesis from the Algorithmic-Level 122(1) Simulation Speed 122(1) Memory 123(6) Verilog Mini-Reference 129(34) Basic Syntax 129(5) Comments 129(1) Identifiers 130(1) Keywords 130(1) Numbers 131(1) Integer Constant 131(2) Real Constant 133(1) Strings 133(1) Declarations 134(3) Net (Wire) 134(1) Module 134(1) Ports 134(1) Parameter 135(1) Local Parameter 136(1) Variable (Reg) 137(1) Statements 137(13) Assignment Statement 137(1) Blocking Assignment 137(1) Non-blocking Assignment 138(1) Continuous Assignment 138(1) Case statement 139(2) If-Else Statement 141(1) Loop Statement 142(1) For Loop 142(1) Repeat Loop 143(1) While Loop 143(1) Null 144(1) Procedure 144(1) Always Procedure 144(2) Initial Procedure 146(1) Module Instantiation 146(1) Port Connection 147(1) Parameter Assignment 147(1) Timing control 148(1) Delay Control 148(1) Event Control 149(1) Timescale Directive 149(1) Wait Statement 150(1) Operators 150(5) Arithmetic 150(1) Bitwise 151(1) Concatenation 151(1) Conditional 152(1) Equality 152(1) Logical 153(1) Reduction 153(1) Relational 154(1) Shift 154(1) Operator Precedence 155(1) System Tasks and Functions 155(4) $display and $write 156(1) File Input and Output 157(1) $fopen 157(1) $feof 157(1) $fgetc 158(1) $fclose 158(1) $fdisplay and $fwrite 158(1) $readmemb and $readmemh 158(1) $signed and $unsigned 159(1) $time 159(1) Common Data Types 159(4) Array 159(1) Integer 160(1) Signed 160(1) Vector 160(3) Index 163