Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

Name: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Author: Sumit Ahuja

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Gebonden, 170 blz. | Engels

Springer New York | 2012e druk, 2011

ISBN13: 9781461408710

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Springer New York 2012e druk, 2011 9781461408710

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This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Specificaties

ISBN13:9781461408710

Taal:Engels

Bindwijze:gebonden

Aantal pagina's:170

Uitgever:Springer New York

Druk:2012

Inhoudsopgave

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.<br>

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