Digital Electronics V1 – Combinational Logic Circuits

<p>Preface ix</p>
<p>Chapter 1. Number Systems 1</p>
<p>1.1. Introduction 1</p>
<p>1.2. Decimal numbers 1</p>
<p>1.3. Binary numbers 2</p>
<p>1.4. Octal numbers 4</p>
<p>1.5. Hexadecimal numeration 5</p>
<p>1.6. Representation in a radix B 6</p>
<p>1.7. Binary–coded decimal numbers 7</p>
<p>1.8. Representations of signed integers 8</p>
<p>1.8.1. Sign–magnitude representation 9</p>
<p>1.8.2. Two s complement representation 10</p>
<p>1.8.3. Excess–E representation 12</p>
<p>1.9. Representation of the fractional part of a number 13</p>
<p>1.10. Arithmetic operations on binary numbers 16</p>
<p>1.10.1. Addition 16</p>
<p>1.10.2. Subtraction 17</p>
<p>1.10.3. Multiplication 18</p>
<p>1.10.4. Division 19</p>
<p>1.11. Representation of real numbers 20</p>
<p>1.11.1. Fixed–point representation 20</p>
<p>1.11.2. Floating–point representation 22</p>
<p>1.12. Data representation 28</p>
<p>1.12.1. Gray code 28</p>
<p>1.12.2. p–out–of–n code 29</p>
<p>1.12.3. ASCII code 31</p>
<p>1.12.4. Other codes 31</p>
<p>1.13. Codes to protect against errors 31</p>
<p>1.13.1. Parity bit 31</p>
<p>1.13.2. Error correcting codes 33</p>
<p>1.14. Exercises 36</p>
<p>1.15. Solutions 38</p>
<p>Chapter 2. Logic Gates 49</p>
<p>2.1. Introduction 49</p>
<p>2.2. Logic gates 50</p>
<p>2.2.1. NOT gate 51</p>
<p>2.2.2. AND gate 51</p>
<p>2.2.3. OR gate 52</p>
<p>2.2.4. XOR gate 52</p>
<p>2.2.5. Complementary logic gates 53</p>
<p>2.3. Three–state buffer 54</p>
<p>2.4. Logic function 54</p>
<p>2.5. The correspondence between a truth table and a logic function 55</p>
<p>2.6. Boolean algebra 57</p>
<p>2.6.1. Boolean algebra theorems 59</p>
<p>2.6.2. Karnaugh maps 65</p>
<p>2.6.3. Simplification of logic functions with multiple outputs 73</p>
<p>2.6.4. Factorization of logic functions 74</p>
<p>2.7. Multi–level logic circuit implementation 76</p>
<p>2.7.1. Examples 77</p>
<p>2.7.2. NAND gate logic circuit 78</p>
<p>2.7.3. NOR gate based logic circuit 80</p>
<p>2.7.4. Representation based on XOR and AND operators 82</p>
<p>2.8. Practical considerations 89</p>
<p>2.8.1. Timing diagram for a logic circuit 90</p>
<p>2.8.2. Static hazard 90</p>
<p>2.8.3. Dynamic hazard 92</p>
<p>2.9. Demonstration of some Boolean algebra identities 93</p>
<p>2.10. Exercises 97</p>
<p>2.11. Solutions 101</p>
<p>Chapter 3. Function Blocks of Combinational Logic 115</p>
<p>3.1. Introduction 115</p>
<p>3.2. Multiplexer 115</p>
<p>3.3. Demultiplexer and decoder 121</p>
<p>3.4. Implementation of logic functions using multiplexers or decoders 127</p>
<p>3.4.1. Multiplexer 127</p>
<p>3.4.2. Decoder 129</p>
<p>3.5. Encoders 130</p>
<p>3.5.1. 4:2 encoder 131</p>
<p>3.5.2. 8:3 encoder 134</p>
<p>3.5.3. Priority encoder 136</p>
<p>3.6. Transcoders 143</p>
<p>3.6.1. Binary code and Gray code 143</p>
<p>3.6.2. BCD and excess–3 code 149</p>
<p>3.7. Parity check generator 155</p>
<p>3.8. Barrel shifter 160</p>
<p>3.9. Exercises 165</p>
<p>3.10. Solutions 173</p>
<p>Chapter 4. Systematic Methods for the Simplification of Logic Functions 203</p>
<p>4.1. Introduction 203</p>
<p>4.2. Definitions and reminders 203</p>
<p>4.2.1. Definitions 204</p>
<p>4.2.2. Minimization principle of a logic function 204</p>
<p>4.3. Karnaugh maps 205</p>
<p>4.3.1. Function of five variables 205</p>
<p>4.3.2. Function of six variables 207</p>
<p>4.3.3. Karnaugh map with entered variable 208</p>
<p>4.3.4. Applications 215</p>
<p>4.3.5. Representation based on the XOR and AND operators 220</p>
<p>4.4. Systematic methods for simplification 220</p>
<p>4.4.1. Determination of prime implicants 221</p>
<p>4.4.2. Finding the constitutive terms of a minimal expression 224</p>
<p>4.4.3. Quine McCluskey technique: simplification of incompletely defined functions 235</p>
<p>4.4.4. Simplification of functions with multiple outputs 235</p>
<p>4.5. Exercises 241</p>
<p>4.6. Solutions 243</p>
<p>Bibliography 257</p>
<p>Index 259</p>